During the manufacture of a semiconductor device such as dynamic random access memories (DRAMs), static random access memories (SRAMs), microprocessors, and logic devices, several structures are commonly formed. For example, contact openings to a conductive layer such as doped monocrystalline silicon wafer, a polycrystalline silicon (polysilicon) layer, or a metal feature through a dielectric layer such as tetraethyl orthosilicate (TEOS) and/or borophosphosilicate glass (BPSG) can be formed. Further, openings are commonly formed within a dielectric layer as an early step in the formation of a container capacitor in a memory device.
FIGS. 1–6 depict a conventional process used during the formation of a semiconductor memory device such as a DRAM to form double-sided storage capacitors and digit line contacts. FIG. 1 depicts a semiconductor wafer substrate assembly comprising a semiconductor wafer 10, field oxide 12, doped wafer areas 13, transistor control gates typically comprising a polysilicon gate 14A and silicide 14B, and surrounding dielectric typically comprising gate oxide 16A, silicon nitride spacers 16B, and capping layer 16C, for example silicon nitride. A conventional device further comprises polysilicon contact pads including pads 18 to which container capacitor storage nodes will be electrically coupled and pads 20 (only one depicted) which will form a portion of a digit line contact to the wafer 10. A dielectric layer 22, for example BPSG, separates the pads. Also depicted is a second layer of dielectric 24 which can be one or more layers of TEOS and/or BPSG. With current technology, layer 24 can be between about 10,000 angstroms (Å) and about 20,000 Å thick. A layer of photoresist 26 defines openings 28 which overlie pads 18 to which the container capacitors will be electrically coupled. The structure of FIG. 1 is exposed to a vertical anisotropic etch which removes the dielectric layer 24 selective to the polysilicon contact pads 18.
FIG. 2 depicts openings 30 in dielectric 24 which result from the etch of the FIG. 1 structure, and the etch forms an opening having first and second cross-sectional sidewalls. Each opening is generally round or oval when viewed from the top down, and the sidewalls are cross-sectional as a round or oval opening will have one continuous sidewall. The etch exposes pads 18, which in turn contact doped regions 13. Pads 18, therefore, decrease the amount of oxide which the etch of the FIG. 1 structure must remove. Without pads 18, the etch would be required to remove the additional thickness of oxide layer 22 to expose doped regions 13.
After forming the openings a blanket layer of polysilicon 32, such as hemispherical silicon grain (HSG) is formed over exposed surfaces including pads 18. Subsequently, the openings are filled with a sacrificial protective material 34 such as photoresist and the HSG and a portion of dielectric 24 are removed, for example using chemical mechanical polishing (CMP). This removes the HSG from the horizontal surface of dielectric 24 to result in the polysilicon structures 32 of FIG. 3. A photoresist mask 36 is formed over the structure to protect the oxide layer between the two container capacitors depicted, then an oxide etch is completed to remove a portion of the exposed oxide, preferably about ⅔ of the thickness, depicted as 40 in FIG. 4. Next, the photoresist layers 34, 36 are removed and blanket layers of silicon nitride 42 (cell nitride) between about 40 Å and about 70 Å thick and top plate polysilicon 44 between about 500 Å and about 2,000 Å thick are formed. A planar layer of BPSG 46, which with current technology has a thickness of about 4,000 Å, is formed and a patterned photoresist layer 48 is formed which defines an opening 50 which will expose digit line contact pad 20.
Subsequently, as depicted in FIG. 5, digit line contact pad 20 is exposed by etching through BPSG 46, top plate polysilicon 44, cell nitride 42, and oxide dielectric 24. The etch, which can comprise one etch or a series of different etches to remove the different materials, must therefore etch through between about 15,000 Å and about 30,000 Å of material to expose contact pad 20. With current technology, the opening is formed to be between about 2,000 Å and about 3,000 Å wide, and thus the opening formed after the etch has an aspect ratio of about 10:1.
Subsequently, the conductive polysilicon top plate 44 is recessed within dielectric 46 and nitride 42 using an isotropic silicon etch. This etch also removes between about 200 Å to about 1,000 Å from exposed polysilicon pad 20, which does not unduly affect the performance of the pad. A conformal dielectric layer is formed, for example using chemical vapor deposition (CVD), and then a spacer etch is completed to form spacers 52 which are approximately 300 Å wide. A digit line plug process is completed to form a plug layer 54, for example comprising polysilicon, tungsten, or a multilayer structure from tungsten and titanium nitride/titanium silicide (TiN/TiSix), having a completed diameter of about 3,000 Å wide. A CMP step is performed to remove the plug layer 54 from the horizontal upper surface of the structure depicted to result in plug 60 of FIG. 6. Next, a digit line runner 62 is formed, for example from aluminum or copper. Wafer processing continues, for example to form various subsequent memory device structures.
Various problems are possible during the manufacturing process using the exemplary conventional process described above and other similar processes. One problem is that the oxide etch to define the digit line plug (see 50, FIG. 4) comes very close to the capacitor bottom plate 32. Thus minor misalignment of the mask 48 can produce a cell having the digit line plug shorted to the capacitor bottom plate. Another disadvantage of the conventional cell described is that the top plate is double-sided on only one portion of the bottom plate. The spacing between the bottom plate and the digit line plug is close enough that forming a double-sided top plate between the digit line plug and the bottom plate is not feasible. Further, it is difficult to etch the digit line contact opening defined by photoresist layer 48 at opening 50 in FIG. 4, as the aspect ratio of the completed opening is about 10:1. It is well known in the art that it is difficult to etch an opening having a high aspect ratio.
A method for forming a capacitor cell and digit line plug which reduces or eliminates various problems and disadvantages with conventional cells would be desirable.